15. Interrupts

This chapter will discuss the overall interrupt architecture of the current system. For more details on please refer to The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Version 1.11.

15.1. Interrupt Concepts

The system has support for the following interrupts: local (including software and timer) and global. Software and timer interrupts are local interrupts generated by the Core Local Interruptor (CLINT) which are directly routed to the hart. The system contains no other local interrupt source.

Global interrupts on the other hand are managed by the Platform-Level Interrupt Controller (PLIC) which are directly routed to the hart via the exteral interrupt source.

By default, all interrupts are handled in machine mode. For harts that support supervisor mode, it is possible to selectively delegate interrupts to supervisor mode.

15.2. Interrupt Entry and Exit

When a RISC-V hart takes an interrupt, the following occurs:

• The value of mstatus.MIE is copied into mstatus.MPIE, and then mstatus.MIE is cleared, effectively disabling interrupts.

• The current PC is copied into the mepc register, and then PC is set to the value of mtvec. In the case where vectored interrupts are enabled, PC is set to mtvec.BASE + 4 × exception code.

• The privilege mode prior to the interrupt is encoded in mstatus.MPP.

At this point, control is handed over to the interrupt handler with interrupts disabled. Interrupts can be re-enabled by explicitly setting mstatus.MIE or by executing an MRET instruction to exit the handler. When an MRET instruction is executed, the following occurs:

• The privilege mode is set to the value encoded in mstatus.MPP.

• The value of mstatus.MPIE is copied into mstatus.MIE.

• The PC is set to the value of mepc.

At this point control is handed back to the program that was under execution when the interrupt was taken.

The Control and Status Registers involved in handling RISC-V interrupts are described in the following section,.

15.3. Interrupt Control Status Registers

The system specific implementation of interrupt CSRs is described below. For a complete description of RISC-V interrupt behavior and how to access CSRs, please refer The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Version 1.11.

15.3.1. Machine Status Register (mstatus)

The mstatus register maintains control of the hart’s current operating state. A summary of the mstatus fields related to interrupts is provided in Table 15.1. Note that this is not a complete description of mstatus. For the full description of mstatus, please refer the The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Version 1.11.

Table 15.1 Machine Status Register (partial)

Bits	Field Name	Attr.	Description
0	Reserved	WPRI
1	SIE	RW	Supervisor Interrupt Enable
2	Reserved	WPRI
3	MIE	RW	Machine Interrupt Enable
4	Reserved	WPRI
5	SPIE	RW	Supervisor Previous Interrupt Enable
6	Reserved	WPRI
7	MPIE	RW	Machine Previous Interrupt Enable
8	SPP	RW	Supervisor Previous Privilege Mode
[10:9]	Reserved	WPRI
[12:11]	MPP	RW	Machine Previous Privilege Mode

Interrupts are enabled by setting the MIE bit in mstatus and by enabling the desired individual interrupt in the mie described in Section 15.3.2.

15.3.2. Machine Interrupt Enable Register (mie)

Individual interrupts are enabled by setting the appropriate bit in the mie register. The mie register is described in Table 15.2.

Table 15.2 MIE register

Bits	Field Name	Attr.	Description
0	Reserved	WPRI
1	SSIE	RW	Supervisor Software Interrupt Enable
2	Reserved	WPRI
3	MSIE	RW	Machine Software Interrupt Enable
4	Reserved	WPRI
5	STIE	RW	Supervisor Timer Interrupt Enable
6	Reserved	WPRI
7	MTIE	RW	Machine Timer Interrupt Enable
8	Reserved	WPRI
9	SEIE	RW	Supervisor External Interrupt Enable
10	Reserved	WPRI
11	MEIE	RW	Machine External Interrupt Enable
[63:12]	Reserved	WPRI

15.3.3. Machine Interrupt Pending (mip)

The machine interrupt pending (mip) register indicates which interrupts are currently pending. The mip register is described Table 15.3.

Table 15.3 MIP register

Bits	Field Name	Attr.	Description
0	Reserved	WIRI
1	SSIP	RW	Supervisor Software Interrupt Pending
2	Reserved	WIRI
3	MSIP	RO	Machine Software Interrupt Pending
4	Reserved	WIRI
5	STIP	RW	Supervisor Timer Interrupt Pending
6	Reserved	WIRI
7	MTIP	RO	Machine Timer Interrupt Pending
8	Reserved	WIRI
9	SEIP	RW	Supervisor External Interrupt Pending
10	Reserved	WIRI
11	MEIP	RO	Machine External Interrupt Pending
[63:12]	Reserved	WIRI

15.3.4. Machine Cause Register (mcause)

When a trap is taken into M-mode, mcause is written with a code indicating the event that caused the trap. The Interrupt bit in the mcause register is set if the trap was caused by an interrupt. The Exception Code field contains a code identifying the last exception

Table 15.4 mcause Register

Bits	Field Name	Attr.	Description
[62:0]	Exception Code	WLRL	A code identifying the last exception.
63	Interrupt	WARL	1 if the trap was caused by an interrupt; 0 otherwise.

Table 15.5 mcause Exception Codes

Interrupt	Exception Code	Description
1	0	Reserved
1	1	Supervisor software interrupt
1	2	Reserved
1	3	Machine software interrupt
1	4	Reserved
1	5	Supervisor timer interrupt
1	6	Reserved
1	7	Machine timer interrupt
1	8	Reserved
1	9	Supervisor external interrupt
1	8	Reserved
1	11	Machine external interrupt
1	≥ 12	Reserved
0	0	Instruction address misaligned
0	1	Instruction access fault
0	2	Illegal instruction
0	3	Breakpoint
0	4	Load address misaligned
0	5	Load access fault
0	6	Store/AMO address misaligned
0	7	Store/AMO access fault
0	8	Environment call from U-mode
0	9	Environment call from S-mode
0	10	Reserved
0	11	Environment call from M-mode
0	12	Instruction page fault
0	13	Load page fault
0	14	Reserved
0	15	Store/AMO page fault
0	≥ 16	Reserved

15.3.5. Machine Trap Vector (mtvec)

mtvec holds the address to which all interrupts trap to. The ISR at the trap address is responsible for reading the mcause values and handling the corresponding trap appropriately.

RISC-V also supports vectoring of interrupts. When vectoring is enabled, interrupts cause the PC to be set to the address in the BASE field plus four times the interrupt cause number. This allows all local interrupts to trap to exclusive trap handlers.

Vectored interrupts are enabled when the MODE field of the mtvec register is set to 1.

Table 15.6 mtvec Register

Bits	Field Name	Attr.	Description
[1:0]	MODE	WARL	MODE determines whether or not interrupt vectoring is enabled. The encoding for the MODE field is described in Table 15.7
[63:2]	BASE	WARL	Interrupt Vector Base Address. Must be aligned on a 128-byte boundary when MODE=1. Note, BASE[1:0] is not present in this register and is implicitly 0.

Table 15.7 MODE field encoding of the mtvec register

Value	Name	Description
0	Direct	All exceptions set PC to BASE
1	Vectored	Asynchronous interrupts set PC to BASE + 4 × cause.
≥ 2	Reserved

15.4. Interrupt Priorities

Individual priorities of global interrupts are determined by the PLIC.

Local interrupts are prioritized as follows, in decreasing order of priority:

• Machine external interrupts

• Machine software interrupts

• Machine timer interrupts

• Supervisor external interrupts

• Supervisor software interrupts

• Supervisor timer interrupts